The metrics are IPC (instructions per cycle), number of instructions and cycles, the number of cycles that were executed in a transaction, the number of transactional cycles that were aborted, the number of started RTM speculations, the number of started HLE speculations and the average number of transactional cycles per transaction (average transaction length). When the % transactional cycles is low the program may not spend much time in critical sections or the locks are not enabled for TSX lock elision. The outputs reports a few metrics for each of the cores and also aggregated metrics for the whole system. The measurement is similar to the Linux "perf stat -T". In this blog I will show a few examples how Intel PCM TSX tool can be used.Ī first step after enabling Intel TSX in the application is to measure basic transactional success. Intel PCM is a simple open-source monitoring API and a collection of sample tools based on it (running on Windows, FreeBSD, MacOS X and arbitrary/old Linux kernels). These capabilities are documented in Intel® 64 and IA-32 Architectures Optimization Reference Manual and already supported by TSX Linux perf profiler and Intel® Performance Counter Monitor (Intel® PCM). ![]() In fact the 4th generation Intel® Core™ processors (with Intel TSX) introduced special hardware monitoring capabilities to measure the success of Intel TSX execution and to provide information about speculation failures. Intel® Transactional Synchronization Extensions ( Intel® TSX - instructions for speculative execution of critical sections protected by locks) are not an exception here. After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technology has been applied correctly and efficiently.
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